In a digital communications system, digital audio data and control information is transmitted in a predetermined serial transmission format such as AES-EBU or CP-340. Both the AES-EBU and CP-340 formats were developed for serial transmission of two channels of both digital audio data and non-audio, or control, data from a transmitter to one or a plurality of receivers.
The AES-EBU and CP-340 formats transmit Manchester encoded digital audio and non-audio data in a series of frames. The digital audio and non-audio data is typically sampled periodically by a source frequency and formed into a left audio or a right audio channel of two's complement data. Two subframes, one for left channel information and a second for right channel information, are transmitted in sequence in any one period of the source frequency. The two subframes may also be collectively referred to as a frame. In the AES-EBU format, each subframe has a length of thirty-two time slots, where each time slot corresponds to a data bit of digital audio or non-audio information. Typically, the first four bits of each subframe are preamble bits. Preamble bits are encoded to synchronize a receiver to the source frequency of the transmitter. The next twenty-four bits transfer audio data information in two's complement form. A next bit is generally referred to as a validity (V) bit. The V bit indicates if the previous audio data information was transmitted to the receiver without any errors. The V bit is a logic zero level when the audio data information is valid and a logic one level when the audio data information was transmitted with errors. Subsequently, a next bit is the user data (U) bit. The U bit contains user data which is associated with either the left or right audio channel. A following bit is the channel status (C) bit. The C bit is used to form a control group of data bits to control transmission of audio and control information. For each one of the left and right audio channels, the control group of data bits is referred to as a channel status block. The channel status block is formed by accessing the C bit of each of 192 successive frames. Typically, the last eight C bits of each block are collectively referred to as the cyclic redundancy check character (CRCC). The CRCC provides information necessary to test for failed reception of the entire block of channel status bits. A start of a block is identified by a special block preamble which replaces a predetermined one of a subframe preamble once every one hundred ninety-two frames. The last bit of a subframe is the parity (P) bit. The P bit indicates even parity of the subframe currently transmitted. Therefore, the P bit is used to easily detect transmission errors and may be used to determine channel reliability.
Both the AES-EBU and CP-340 formats are commonly used for transmitting digital audio and non-audio data from a transmitter to a digital signal processor. Typically, the digital data is provided to an interface receiver where it is modified to a form in which it may be used by the digital signal processor. In an interface transceiver, audio and non-audio data is received and converted into bytes of digital information. The bytes of digital information are then provided to the digital signal processor. Generally, audio and non-audio data corresponding to a left channel is transmitted first, and audio and non-audio data corresponding to a right channel is subsequently transmitted. Information typically required for the digital signal processor to interface and communicate properly with the digital audio source must also be transferred to the interface transceiver.
In particular, control and status information must be provided to the digital signal processor from an interface transceiver. The control and status information which should be monitored is determined by the user of the communications system and may be application dependent, as well. For example, the control and status information may be used to indicate whether or not a plurality of pins of the interface transceiver is programmed, if the signal input to a phase lock loop within the interface transceiver has too high or too low of a frequency, or even if the channel status bits have been transmitted correctly.
Typically, control and status information must first be transferred from the interface transceiver to the digital signal processor via a plurality of either data or control pins. Therefore, in addition to a modulation circuit generally required for transmission of serial data in either the AES-EBU or CP-340 format, additional circuitry must also be implemented within the interface transceiver to modulate status information provided to the digital signal processor by the plurality of either data or control pins. Additionally, circuitry must also be implemented to receive control information from the digital signal processor to the interface transceiver. Although the added circuitry and the dedicated address or data pins are necessary, both generally add to the overhead costs of the interface transceiver.
Additionally, when interfacing between a digital signal processor and either a digital audio source or a digital audio sink, programming information to control operation of the interface transceiver is required and may be provided by the digital signal processor. Programming information is necessary for the interface transceiver to execute a plurality of functions. For example, programming information may provide control and data for programmable output pins or enable multiplexers to select predetermined programmable clock outputs. Programming information may also be necessary to select digital audio inputs and to determine the clock sources necessary for a phase lock loop circuit or a modulator clock source within the interface transceiver.
Like the transfer of control or status information, programming information is generally transmitted from the digital signal processor to the plurality of data input pins of the interface transceiver using a standard data/address chip select interface. Again, the plurality of data and address input pins of the interface transceiver tends to significantly increase the overhead costs of the interface transceiver. As well, during transmission of both status and programming information, the digital audio data transmitted serially from the digital audio source may be interrupted and remain suspended until the status and programming information is provided to the receiver portion of the transceiver. The time necessary to transmit digital audio data is subsequently lengthened by the time necessary to transmit the status and programming information.
To avoid interrupting a flow of digital audio data, some current implementations of interface transceivers minimize the amount of status information transferred. For example, a single status signal indicating phase lock loop information may be the only status information provided to the digital signal processor. However, although the flow of digital audio data is interrupted for a minimal time, status information concerning operation of the transceiver is not provided to the digital signal processor.
Because current implementations of communication systems typically require status and programming information values necessary for proper operation to respectively either be provided by a plurality of output pins of the interface transceiver or be provided to a plurality of input pins of an interface transceiver, the overhead costs of the interface transceiver are increased. Also adding to the overhead is the typical requirement of needing to be able to interrupt transmission of serial digital data. The efficiency of the interface transceiver is also decreased by the interruption of transmission of the digital audio and non-audio data. Therefore, a need exists to transmit status and programming information without interrupting the transmission of digital audio data. Additionally, a need exists for the status and programming information to be provided to a minimal number of input pins of the interface transceiver without sacrificing either speed or efficiency.